Completed Winter 2020

Design of an Academic RISC-V Core

Bachelor's Thesis in Computer Engineering focused on designing a simple RISC-V processor core and implementing it in an FPGA for educational and research purposes.

Duration

Winter 2020

Team Size

1 members

Role

Hardware Designer & Developer

Technologies

RISC-VVerilogFPGADigital DesignComputer ArchitectureHardware Description Language
💻 Code 📚 Documentation

Overview

Bachelor's Thesis project in Computer Engineering focusing on the design and implementation of an academic RISC-V processor core for educational and research applications.

Project involved complete processor design from instruction set architecture analysis through RTL implementation and FPGA synthesis.

Implementation demonstrates fundamental computer architecture principles and provides a practical platform for understanding processor design concepts.

Specifications

Project Details

Degree

Bachelor's in Computer Engineering

Architecture

RISC-V ISA

Implementation

Hardware Description Language

Language

Verilog HDL

Target

FPGA Implementation

Purpose

Academic & Research

Technical Specifications

ISA

RV32I Base Integer Instruction Set

Pipeline

Single-cycle implementation

Memory

Harvard architecture

Registers

32 general-purpose registers

Data Width

32-bit word size

Synthesis

FPGA-optimized design

Key Features

Processor Features

  • ▸ Complete RV32I instruction set support
  • ▸ 32 general-purpose registers
  • ▸ Harvard memory architecture
  • ▸ Single-cycle execution model
  • ▸ Configurable memory interfaces
  • ▸ Debug and monitoring capabilities

Development Tools

  • ▸ Verilog HDL implementation
  • ▸ FPGA synthesis and implementation
  • ▸ Simulation and verification testbenches
  • ▸ Assembly language programming support
  • ▸ Performance analysis tools
  • ▸ Documentation and tutorials

Development Process

1

Architecture Analysis

Studied RISC-V instruction set architecture and defined processor specifications for academic implementation.

2

RTL Design

Designed processor datapath and control unit using Verilog HDL, implementing complete RV32I instruction set.

3

Verification & Testing

Developed comprehensive testbenches and verification procedures to validate processor functionality.

4

FPGA Implementation

Synthesized design for FPGA implementation and conducted performance analysis and optimization.

Results & Impact

Achievements

  • ✓ Successfully implemented complete RV32I processor
  • ✓ Achieved functional FPGA implementation
  • ✓ Developed comprehensive verification suite
  • ✓ Created educational documentation and examples
  • ✓ Open-sourced project for academic use
  • ✓ Gained expertise in digital design and computer architecture

Applications

  • ● Computer engineering education
  • ● Processor design learning platform
  • ● Research and development tool
  • ● FPGA-based embedded systems
  • ● Academic coursework and projects
  • ● Open-source hardware community
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